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L4992
TRIPLE OUTPUT POWER SUPPLY CONTROLLER
DUAL PWM BUCK CONTROLLERS (3.3V and 5.1V) 12V/120mA LINEAR REGULATOR DUAL SYNCH RECTIFIERS DRIVERS 96% EFFICIENCY ACHIEVABLE 50A (@ 12V) STAND BY CONSUMPTION 5.5V TO 25V SUPPLY VOLTAGE EXCELLENT LOAD TRANSIENT RESPONSE DISABLE PULSE SKIPPING FUNCTION POWER MANAGEMENT: - UNDER AND OVERVOLTAGE OUTPUT DETECTION - POWER GOOD SIGNAL - SEPARATED DISABLE THERMAL SHUTDOWN PACKAGE: TQFP32 APPLICATION NOTEBOOK AND SUBNOTEBOOK COMPUTERS PEN TOP AND PORTABLE EQUIPMENT COMMUNICATING COMPUTERS DESCRIPTION The L4992 is a sophisticated dual PWM stepdown controller and power monitor intended for Notebook computer and/or battery powered equipment. The device produces regulated +3.3V, +5.1V and 12V supplies for use in portable SYSTEM BLOCK DIAGRAM
3.3V 5.5V to 25V
TQFP32 ORDERING NUMBER: L4992
and PCMCIA applications. The internal architecture allows to operate with minimum external components count. A very high switching frequency (200/300 KHz or externally synchronizable) optimizes their physical dimensions. Synchronous rectification and pulse skipping mode for the buck sections optimise the overall efficiency over a wide load current range (96% efficiency @1A/5.1V and 93% efficiency @ 0.05A/5.1V. The two high performance PWM controllers for +3.3V and +5.1V lines are monitored for overvoltage, undervoltage and overcurrent conditions. On detection of a fault, a POWER GOOD signal is generated and a specific shutdown procedure takes place to prevent physical damage and data corruption. A disable function allows to manage the output power sections separately, optimising the quiescent consumption of the IC in stand-by conditions.
L4992
POWER SECTION
5.1V
SYNC
12V LDO 5.1V LDO POWER MANAGEMENT & SYSTEM SUPERVISOR 3.39V REF POWER GOOD
P MEMORY PERIPHERALS
D96IN429A
March 1998
1/26
L4992
ABSOLUTE MAXIMUM RATINGS
Symbol VIN VI IIN IOUT TJ Parameter Power Supply Voltage on VIN Maximum Pin Voltage to Pins 1, 24, 25, 32 Input Current Except V13IN and VIN Output Current Digital Output Junction Temperature Value 0 to 25 -0.5 to (VIN +5) -1 to +1 -15 to +15 -55 to 150 Unit V V mA mA C
THERMAL DATA
Symbol RTH J-amb Parameter Thermal Resistance Junction -Ambient Value 60 Unit C/W
PIN CONNECTION (Top view)
H5GATE R5GATE R3GATE H3GATE PGND5 PGND3 H5SRC H3SRC
32 31 30 29 28 27 26 25 H5STRAP VIN REG5 V5SW V5SNS I5SNS COMP5 SOFT5 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
CRST RUN5 VREF SGND OSC PWROK NOSKIP RUN3
24 23 22 21 20 19 18 17
H3STRAP (*) REG12 V13IN V3SNS I3SNS COMP3 SOFT3
D96IN377
(*)TO BE CONNECTED TO PIN13
BLOCK DIAGRAM
SOFT5 8 SLOPE I5SNS V5SNS COMP5 6 5 7 + + + 1 VREF OVER CURRENT COMPARATOR + Hside CONTROL LOGIC ZERO CROSSING COMPARATOR + PULSE SKIPPING COMPARATOR + ERROR SUMMING SOFT SOFT3 17 SOFT ERROR SUMMING + SLOPE 19 20 18 I3SNS V3SNS COMP3
I5SNS V5SNS V3SNS I3SNS
+ +
OVER CURRENT COMPARATOR + ZERO CROSSING COMPARATOR + PULSE SKIPPING COMPARATOR + -
VREF 24
H5STRAP
H3STRAP
H5GATE
32
Hside CONTROL LOGIC
25
H3GATE
H5SRC
31 REG5 30 29
26 REG5 27 28
H3SRC
R5GATE PGND5 REG5
Lside
Lside
R3GATE PGND3
3 LINEAR REGULATOR OVERVOLT COMPARATOR + SWITCH COMPARATOR V5SNS VREF 4.7V POWER MANAGEMENT & SYSTEM SUPERVISOR UNDERVOLT COMPARATOR
13V UV Comp + 13V
21
V13IN
W5SW VIN
4 2
+ -
22 REG12 LDO 15
REG12
VREF
12
VREF BUFFER
+ VREF 16 RUN3
OSCILLATOR & SYNCHRONIZATION 11 RUN5 10 PWROK 14 NOSKIP 9 CRST
OSC
SGND
13
D96IN375
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L4992
PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 Name H5STRAP VIN REG5 V5SW V5SNS I5SNS COMP5 SOFT5 CRST PWROK RUN5 VREF SGND NOSKIP OSC RUN3 SOFT3 COMP3 I3SNS V3SNS V13IN REG12 SGND H3STRAP H3GATE H3SRC R3GATE PGND3 PGND5 R5GATE H5SRC H5GATE Description +5.1V section bootstrap capacitor connection Device supply voltage. From 5.5 to 25V +5V regulator supply. Used mainly for bootstrap capacitors. It should be bypassed to ground. Alternative device supply voltage. When the +5.1V section is operating, the device is no longer powered through VIN but through this pin. This pin connects to the (-) input of the +5.1V internal current sense comparator This pin connects to the (+) input of the +5.1V internal current sense comparator Feedback input for the +5.1V section. Soft-start input of the +5.1V section. The soft-start time is programmed by an external capacitor connected between this pin and SGND. Approximately, 1ms/nF @ full load. Input used for start-up and shut-down timing. A capacitor defines a time of 2ms/nF. Power-good diagnostic signal. This output is driven high when both switching sections are enabled and running properly, after a delay defined by the CRST capacitor. Control input to enable/disable the 5.1V section. A high level (>2.4V) enables this section, a low level (<0.8V) shuts it down Internal +3.39V high accuracy voltage generator. It can source 5mA to external load. Bypass to ground with a 4.7F capacitor to reduce noise. Signal ground. Reference for internal logic circuitry. It must be routed separately from high current returns. Pulse skipping mode control. A high level (>2.4V) disables pulse skipping at low load current, a low level (<0.8V) enables it. Oscillator frequency control: connect to 2.5V to select 300KHz operation, to ground or to 5V for 200KHz operation. A proper external signal can synchronize the oscillator Control input to enable/disable the +3.3V section. A high level (>2.4V) enables this section, a low level (>0.8V) shuts it down. Soft-start input for the 3.3V section. The soft-start time is programmed by an external capacitor connected between this pin and GND. Approximately, 1ms/nF @full load. Feedback input for the +3.3V section This pin connects to the (+) input of the +3.3V internal current sense comparator This pin connects to the (-) input of the +3.3V internal current sense comparator 12V regulator input supply voltage, included between 13 and 20V. This voltage can be supplied by a flyback winding on +3.3V inductor 12V regulator output voltage. It can source up to 150mA to an external load To be connected to pin 13 +3.3V section bootstrap capacitor connection Gate- driver output for the +3.3V high-side N-MOS +3.3V high-side N-MOS source connection Gate- driver output for the +3.3V low- side N-MOS (synchronous rectifier). Current return for +3.3V section drivers Current return for +5.1V section drivers Gate-driver output for the +5.1V low-side N-MOS (synchronous rectifier). +5.1V high-side N-MOS source connection Gate-driver output for the +5.1V high-side N-MOS
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L4992
ELECTRICAL CHARACTERISTICS (VIN = 12V; TJ = 25C; VOSC = GND; unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
DC CHARACTERISTICS
VIN I2 Input Supply Voltage Operating Quiescent Current 5.5 R5GATE = R3GATE = OPEN H5GATE = H3GATE = OPEN RUN3 = RUN5 = REG5 (DRIVERS OFF) RUN3 = RUN5 = GND VIN = 12V VIN = 20V 50 60 25 1.35 V mA
I2
Stand-By Current
100 120
A
+5.1V PWM CONTROLLER SECTION
V5OUT (*) V6 - V5 V6 - V5 V5 V5SNS Feedback Voltage Over-Current Threshold Voltage Pulse Skipping Mode Thereshold Voltage Over Voltage Threshold ON V5SNS Under Voltage Threshold ON V5SNS VIN = 5.5 to 20V; VI5SNS - VV5SNS = 0 to 70mV VSOFT5 = 4V VIN > 6.8V VIN < 5.8V 4.85 80 14 7 5.35 4.54 5.13 100 26 13 5.55 4.69 5.25 120 38 19 5.77 4.87 V mV mV mV V V
+3.3V PWM CONTROLLER SECTION
V3OUT (*) V19 - V20 V19 - V20 V20 V3SNS Feedback Voltage Over Current Threshold Voltage Pulse Skipping Mode Threshold Voltage Over Voltage Threshold ON V3SNS Under Voltage Threshold ON V3SNS VIN = 5.5 to 20V; VI3SNS - VV3SNS = 0 to 70mV VSOFT3 = 4V VIN = 5.5 to 20V; 3.285 80 14 3.55 3.02 3.39 100 26 3.7 3.14 3.495 120 38 3.85 3.27 V mV mV V V
PWM CONTROLLERS CHARACTERISTICS (BOTH SECTIONS)
FOSC V15 TOFF TOV TUV I8, I17 V8, V17 Switching Frequency Accuracy Voltage Range for 300kHz Operation Dead Time Overvoltage Propagation Time Undervoltage Propagation Time Soft Start Charge Current Soft Start Clamp Voltage V5SNS to PWROK or V3SNS to PWROK V5SNS to PWROK or V3SNS to PWROK 3.2 4 4 OSC = REG5/2 OSC = 0 or REG5 255 170 2.4 300 375 300 200 345 230 2.6 450 1.25 1.5 4.8 kHz kHz V ns s s A V
(*) Guaranteed by design, not tested in production
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L4992
ELECTRICAL CHARACTERISTICS (Continued)
Symbol Parameter Test Condition Min. Typ. Max. Unit
HIGH AND LOW SIDE GATE DRIVER (BOTH SECTIONS)
I25, I27, I32, I30 RH RL VOH VOL TCC Source Output Peak Current Sink Output Peak Current RDSON Resistance (or Impedance) RDSON resistance (or Impedance) Output High Voltage Output Low Voltage Cross-Conduction Delay CLOAD = 1nF CLOAD = 1nF Driver OUT HIGH Driver OUT LOW HSTRAP = REG5 ISOURCE = 10mA; HSRC = GND HSTRAP = REG5 ISINK = 10mA HSRC = GND 30 75 4.40 5.3 0.2 0.2 0.5 0.5 7 5 5.61 0.5 130 A A V V ns
12V LINEAR REGULATOR SECTION
V21 V22 I22 VCP Input Voltage Range Output Voltage Current Limiting Short Circuit Current Input Voltage Clamp "One Shot" Activation Threshold "One Shot" Pulse I22 = 0 to 120mA VREG12 = 12V VREG12 = 0V ICLAMP = 100A V13IN Falling 13 11.54 120 150 16 12.88 13.7 14.52 1.5 12.0 20 12.48 V V mA mA V V s
INTERNAL REGULATOR (VREG5) AND REFERENCE VOLTAGE
V3 I3 VREG5 Output Voltage Total Current Capability Switch-Over Threshold Voltage V12 Reference Voltage VIN = 5.5 to 20V ILOAD = 1 to 5mA I12 Source Current at Reference Voltage VIN = 5.5 to 20V ILOAD = 0 to 5mA VREG5 = 5.3V VREG5 = 6V 4.5 25 70 4.3 3.35 3.32 5 5.3 5.61 V mA 4.53 3.39 3.39 4.7 3.43 3.46 V V V mA
POWER GOOD AND ENABLE FUNCTION
V16, V11 V16, V11 T10 T27, T30 RUN3, RUN5, Enable Voltage RUN3, RUN5, Disable Voltage Power Good Delay Shutdown Delay Time before Low Side Activation (Except Over-Voltage Fault) CRST Timing Rate Power Good High Level Power Good LowLevel SYNCHRONIZATION Synchronisation Pulse Width Synchronisation Input Voltage (Falling Edge Transition) HIGH LEVEL LOW LEVEL CCRST = 100nF CCRST = 100nF, 2.4 160 160 200 200 0.8 240 240 V V ms ms
2 IPWROK = 40A IPWROK = 320A 400 5 4.1 0.4
ms/nF V V ns V
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L4992
DETAILED FUNCTIONAL DESCRIPTION In the L4992 block diagram six fundamental functional blocks can be identified: 3.3V step-down PWM switching regulator (pins 17 to 20, 24 to 27). 5.1V step-down PWM switching regulator (pins 1, 4 to 8, 30 to 32). 12V low drop-out linear regulator (pins 21,22). 5V low drop-out linear regulator (pin 3). 3.3V reference voltage generator (pin 12). Power Management section (pins 9 to 11, 14,16). The chip is supplied through pin VIN (2), typically by a battery pack or the output of an AC-DC adapter, with a voltage that can range from 5.5 to 25V. The return of the bias current of the device is the signal ground pin SGND (13), which references the internal logic circuitry. The drivers of the external MOSFET's have their separate current return for each section, namely the power ground pins PGND3 (28) and PGND5 (29). Take care of keeping separate the routes of signal ground and the two power ground pins when laying out the PCB (see "Layout and grounding" section). The two PWM regulators share the internal oscillator, programmable or synchronizable through pin OSC (15). +3.3V AND +5.1V PWM REGULATORS Each PWM regulator includes control circuitry as well as gate-drive circuits for a step-down DC-DC converter in buck topology using synchronous rectification and current mode control. The two regulators are independent and almost identical. As one can see in the Block Diagram, they share only the oscillator and the internal supply and differ for the pre-set output voltages and for the control circuit that links the +3.3V section to the operation of the 12V linear regulator (see the relevant section). Each converter can be turned on and off independently: RUN3 and RUN5 are control inputs which disable the relevant section when a low logic level (below 0.8 V) is applied and enable its operation with a high logic level (above 2.4 V). When both inputs are low the device is in stand-by condition and its current consumption is extremely reduced (less than 120A over the entire input voltage range). Oscillator The oscillator, which does not require any external timing component, controls the PWM switching frequency. This can be either 200 or 300 kHz, depending on the logic state of the control pin OSC, or else can be synchronized by an external oscillator. If OSC is grounded or connected to pin REG5 (5V) the oscillator works at 200kHz. By connecting OSC to a 2.5 V voltage, 300 kHz operation will be selected. Instead, if pin OSC is fed with an external signal like the one shown in fig. 1, the oscillator will be synchronized by its falling edges. Considering the spread of the oscillator, synchronization can be guaranteed for frequencies above 230kHz. Even though a maximum frequency value is in practice imposed by efficiency considerations it should be noticed that increasing frequency too much arises problems (noise, subharmonic oscillation, etc.) without significant benefits in terms of external component size reduction and better dynamic performance. The oscillator imposes a time interval (300 ns min.), during which the high-side MOSFET is definitely OFF, to recharge the bootstrap capacitor (see "MOSFET's Drivers" section). This, implies a limit on the maximum duty cycle (88.5% @ fsw = 300kHz, 92.6% @ fsw = 200kHz, worst case) which, in turn, imposes a limit on the minimum operating input voltage. PWM regulation The control loop does not employ a traditional error amplifier in favour of an error summing comparator which sums the reference voltage, the feedback signal, the voltage drop across an external sense resistor and a slope compensation ramp (to avoid subharmonic oscillation with duty cycles greater then 50%) with the appropriate signs. The output latch of both controllers is set by every pulse coming from the oscillator. That turns off the low-side MOSFET (synchronous rectifier) and, after a short delay (typ. 75 ns) to prevent cross-conduction, turns on the high-side one, thus allowing energy to be drawn from the input source and stored in the inductor.
6/26
L4992
DETAILED FUNCTIONAL DESCRIPTION (continued) Figure 1: Synchronization signal and operation.
OSC 5V 400ns min.
0V H5GATE
t
t H3GATE
D97IN574
t
Figure 2: L4992 Control Loop.
VIN HSTRAP CLOCK S Q L REG5 Co R _ Q ESR
+ -
Rsense
Ro
SLOPE COMP.
Rf
E.S.
+ +
Cf VREF
The error summing, by comparing the above mentioned signals, determines the moment in which the output latch is to be reset. The high-side MOSFET is then turned off and the synchronous rectifier is turned on after the appropriate delay (typ. 75 ns), thus making the inductor current recirculate. This state is maintained until the next oscillator pulse. With reference to the schematic of fig. 2, the open-loop transfer function of such a kind of control system, under the assumption of an ideal slope compensation, is: F(s) = A 1 + s ESR CO RO Rsense (1 + s RO CO) (1 + s RF CF)
where A is the gain of the error summing comparator, which is 2 by design. The system is inherently very fast since it tends to correct output voltage deviations nearly on a cycle-bycycle basis. Actually, in case of line or load changes, few switching cycles can be sufficient for the transient to expire. The operation above illustrated is modified during particular or anomalous conditions. Leaving out other circumstances (described in "Protections" section) for the moment, consider when the load current is low enough or during the first switching cycles at start-up: the inductor current may become discontinuous, that is it is zero during the last part of each cycle. In such a case, a "zero current comparator" detects the event and turns off the synchronous rectifier, avoiding inductor current reversal and reproducing the natural turn-off of a diode when reverse biased. Both MOSFET's stay in off state until the next oscillator pulse.
7/26
L4992
DETAILED FUNCTIONAL DESCRIPTION (continued) Synchronous rectification. Very high efficiency is achieved at high load current with the synchronous rectification technique, which is particularly advantageous because of the low output voltage. The low-side MOSFET, that is the synchronous rectifier, is selected with a very low on-resistance, so that the paralleled Schottky diode is not turned on, except for the small time in which neither MOSFET is conducting. The effect is a considerable reduction of power loss during the recirculation period. Although the Schottky might appear to be redundant, it is not in a system where a very high efficiency is required. In fact, its lower threshold prevents the lossy body-diode of the synchronous rectifier MOSFET from turning on during the above mentioned dead-time. Both conduction and reverse recovery losses are cut down and efficiency can improve of 1-2% in some cases. Besides a small diode is sufficient since it conducts for a very short time. As for the 3.3V section only, the synchronous rectifier is also involved in the 12 V linear regulator operation (see the relevant section). See also the "Power Management" to see how both synchronous rectifiers are used to ensure zero voltage output in stand-by conditions or in case of overvoltage. Pulse-skipping operation. To achieve high efficiency at light load current as well, under this condition the regulators change their operation (unless this feature is disabled): they abandon PWM and enter the so-called pulse-skipping mode, in which a single switching cycle takes place every many oscillator periods. The "light load condition" is detected when the voltage across the external sense resistor (VRsense) does not exceed 26mV while the high-side MOSFET is conducting. When the reset signal of the output latch comes from the error summing comparator while VRsense is below this value, it is ignored and the actual reset is driven as soon as VRsense reaches 26mV. This gives some extra energy that maintains the output voltage above its nominal value for a while. The oscillator pulses now set the output latch only when the feedback signal indicates that the output voltage has fallen below its nominal value. In this way, most of oscillator pulses is skipped and the resulting switching frequency is much lower, as expressed by the following relationship: fps = K R2 Vout sense Iout Vout 1 - L Vin Figure 3: Pulse-skipping threshold vs. input voltage (+5.1V section only).
where K = 3.2 103 and fps is in Hz. As a result, the losses due to switching and to gate-drive, which mostly account for power dissipation at low output power, are considerably reduced. The +5.1V section can work with the input voltage very close to the output one, where the current waveform may be so flat to prevent pulse-skipping from being activated. To avoid this, the pulse-skipping threshold (of the +5.1V section only) is roughly halved at low input voltages, as shown in fig. 3. Under this condition, in the above formula the constant K becomes 12.8 103. When in pulse-skipping, the output voltage is some ten mV higher than in PWM mode, just because of its mode of operation. If this "load regulation" effect is undesirable for any reason, the pulse skipping feature can be disabled (see "Power Management" section) to the detriment of efficiency at light load.
Vth 26 mV
13 mV
5.5V 5.8V
6.3V
20V
Vin
MOSFET's drivers To get the gate-drive voltage for the high-side N-channel MOSFET a bootstrap technique is employed. A capacitor is alternately charged through a diode from the 5V REG5 line when the high-side MOSFET is OFF and then connected to its gate-source leads by the internal floating driver to turn the MOSFET on. The REG5 line is used to drive the synchronous rectifier as well, and therefore the use of low-threshold
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L4992
DETAILED FUNCTIONAL DESCRIPTION (continued) MOSFET's (the so-called "logic-level" devices) is highly recommended. The drivers are of "dynamic" type, which means they do not give origin to current consumption when they are in static conditions (ON or OFF), but only during transitions. This feature is aimed at minimizing the power consumption of the device even during stand-by when both low-side MOSFET's are ON. Protections Each converter is fully protected against fault conditions. A monitoring system checks for overvoltages of the output, quickly disabling both converters in case such an event occurs. This condition is latched and to allow the device to start again either the supply voltage has to be removed or both RUN3 and RUN5 pins have to be driven low. Undervoltage conditions are detected as well but do not cause interruption of the operation of the converters. Only PWROK signal (at pin 10) reveals the anomaly with a low output level. If the chip overheats (above 135 C typ.) the device stops operating as long as the temperature falls below a safe value (105 C typ.). The overtemperature condition is signalled by a low level on PWROK as well. A current limitation comparator prevents from excessive current in case of overload or short-circuit. It intervenes as the voltage VRsense exceeds 100 mV, turning off the high-side switch before the error summing does. By the way, this also gives the designer the ability to program the maximum operating current by selecting an appropriate sense resistor. This pulse-by-pulse limitation gives a quasi-constant current characteristic. If a "folded back" characteristic, like the one shown in Fig. 4a, is desired the external circuit of Fig. 4b can be used. The circuits acts on the current limitation and is extremely simple and cheap. The advantage of such a technique i that a short circuit will cause a current much lower than the maximum to flow. Th e stress of the power components will be very little and no overheating will occur. The part values shown in Fig. 4b produce IFOLD = 1A in the Demo Board (see the relevant section). Inrush current at start-up is reduced with soft-start. An external capacitor (one for each converter) is charged by an internal 4A current generator and its linearly ramping voltage increases the setpoint of the current limit comparator, starting from zero up to the final value of 100 mV. Thus duty cycle reaches gradually its steady-state value and dangerous current peaks as well as overshoots of the output voltage are avoided. +12 V LINEAR REGULATOR The +12V Linear regulator is capable of delivering up to 120 mA to an external load through pin REG12. It is supplied from pin V13IN which accepts voltages included in the range of 13 to 20V. If the application works with input voltages included between 14 and 20V, the supply for the regulator can be obtained directly from the input source. If such is not the case, the most convenient way to get the supply is to use an auxiliary winding on the 3.3 V section inductor with a catch diode, Ds, and a filter capacitor, Cs, as shown in fig. 5. This winding delivers energy to pin V13IN during the recirculation period of each switching cycle with a voltage determined by the turns ratio n and little dependent on the input voltage. Figure 4.
VIN
32(25) L 31(26) 30(27) VO VREF-VF-0.1 Rsense 5V(3.3V)
CO 1N4148
L4992
12
6.8K (3.9K) 6(19) IFOLD Imax IO 5(20) (b)
100
(a)
D98IN815
9/26
L4992
DETAILED FUNCTIONAL DESCRIPTION (continued) An auxiliary winding could be used also on the choke of the +5.1V section, either to power the +12V linear regulator or to derive a further supplemental output, however the 3.3 V section has been provided with some features aimed at ensuring a proper operation under all circumstances. For a correct operation of the regulator, the voltage at pin V13IN must not be too low. The flyback connection of the two windings ensures a well regulated voltage, provided there is good magnetic coupling. The coupled inductors configuration, however, is not able to sustain the auxiliary voltage if the main output is lightly loaded: the secondary voltage drops and the system goes out of regulation. To overcome this problem, when the V13IN voltage falls below a certain threshold (13.7 V +/- 5%) because of too light a load on the 3.3V section, the relevant synchronous rectifier is turned on for 1.5 s max. during the interval in which the inductor current is zero ("one-shot" feature, see fig. 6). In this way, the inductor current reverses and draws from the output capacitor energy which is forward transferred to the auxiliary output. In case the 3.3V section is working at full load and the linear regulator is lightly loaded, the voltage at pin V13IN can exceed the expected value. In fact, Ds and Cs act as a peak-holding circuit and V13IN is influenced by the voltage spikes at switching transients. An internal clamp limits the voltage but, in case of intervention, the chip power dissipation will rise. When the 3.3V regulator is disabled, the linear regulator is disabled as well and is placed in a low-power mode to reduce device consumption. Figure 5: 12V regulator supply with auxiliary winding.
DS to V13IN
n CS 1 3.3V
D97IN575
Figure 6: "One shot" feature to sustain V13IN voltage.
H3GATE
t 1.5s L3GATE
t IL
t V13IN
13.7V
D97IN576A
t
10/26
L4992
DETAILED FUNCTIONAL DESCRIPTION (continued) +5 V LINEAR REGULATOR & +3.3 V REFERENCE VOLTAGE GENERATOR This low drop-out regulator powers almost all the internal circuitry, that is the +3.3V reference voltage generator, amplifiers, comparators, digital logic, and MOSFET drivers. Its output is externally available through pin REG5. The typical external use of this generator is to charge the bootstrap capacitors used to produce the gatedrive voltage for the high-side MOSFET's of both PWM converters. At start-up and when the 5V section is not operating, this regulator is powered by the chip input voltage. To reduce power consumption, the linear regulator is turned off and the REG5 pin is internally connected to the 5V PWM regulator output via V5SW pin, when the 5V PWM regulator is active and its output voltage is above the switchover threshold, 4.5V. The 5V regulator is always active, even if both PWM regulators are disabled, as long as power is applied to the chip. The 3.3V reference voltage generator, which is active only when either PWM converter is enabled, provides comparison levels for threshold detection and device operation. It is allowed to source up to 5mA to an external load from its buffered output, externally available through pin VREF. If either REG5 or VREF does not deliver the correct voltage, the device is shut down.
POWER MANAGEMENT The L4992 is provided with some control pins suitable to perform some functions which are commonly used or sometimes required in battery-operated equipment. Besides, it features controlled timing sequences in case of turn-on/off and device shutdown for a safe and reliable behaviour under all conditions. As above mentioned, RUN3 and RUN5 pins allow to disable separately both PWM converters by means of logic signals (likely coming from a P) as mentioned earlier. NOSKIP can disable the pulse-skipping feature: when it is held high neither of the PWM regulators is allowed to enter this kind of operation. The PWROK output signal drives low immediately when either PWM regulator output falls below its own undervoltage threshold or when either of them is disabled. It is high when both regulator run properly. A capacitor connected between CRST and ground fixes a time, in the order of 2ms/nF, which delays the transition low-high of PWROK. This happens at start-up or after recovering an undervoltage condition, provided both RUN3 and RUN5 are high. The delay starts from the moment in which the output voltage has reached its correct value for both sections. The same delay intervenes also in another circumstance: when a section is disabled (because its RUN is driven low or owing to a thermal shutdown), the relevant synchronous rectifier is turned on after the above delay in order to make sure that the load is no longer supplied. This delay, however, does not intervene in case of overvoltage: the synchronous rectifier is immediately turned on after the shutdown, thus acting as a built-in "crowbar". All these timing sequences are illustrated in Fig 7.
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L4992
DETAILED FUNCTIONAL DESCRIPTION (continued) Figure 7: L4992 controlled timing sequences.
RUN3 t VOUT3 t t VOUT3 H3GATE t t RUN5 R3GATE t t VOUT5 PWROK t RUN5 t PWROK t a) TURN-ON TIMING SEQUENCE H5GATE t RUN3 t VOUT3 t H3GATE t R3GATE t CRST t PWROK t RUN5 t VOUT5 t H5GATE t R5GATE t c) SHUTDOWN TIMING SEQUENCE (2) d) OVP TIMING SEQUENCE R5GATE
D97IN577
RUN3
CRST t
t CRST
t VOUT5 t
R5GATE t b) SHUTDOWN TIMING SEQUENCE (1)
VOUT3 t H3GATE t R3GATE t CRST
PWROK t VOUT5 t H5GATE t
t
12/26
L4992
DESIGN PROCEDURE Basically, the application circuit topology is fixed, and the design procedure concerns only the selection of the component values suitable for the voltage and current requirements of the specific application. The design data one needs to know are therefore: Input voltage range: the minimum (Vinmin) and the maximum (Vinmax) voltage under which the application is expected to operate; Maximum load current for each of the three sections: - Iout3 for the +3.3V section; - Iout5 for the +5.1V section: - Iout12 for the +12V section; Maximum peak-to-peak ripple amplitude of the output voltage for each switching section: - Vrpp3 for the +3.3V section; - Vrpp5 for the +5.1V section; The operating frequency fsw (200/300 kHz or externally synchronized). It is worth doing some preliminary considerations. The selection of the switching frequency depends on the requirements of the application. If the aim is to minimize the size of the external components, 300 kHz will be chosen. For low input voltage applications 200 kHz is preferred, since it leads to a higher maximum duty cycle. As for the switching regulators, the inductance value of the output filter affects the inductor current ripple: the higher the inductance the lower the ripple. This implies a lower current sense resistor value (for a given Iout), lower core losses and a lower output voltage ripple (for a given output capacitor) but, on the other hand, more copper losses and a worse transient behaviour due to load changes. Usually the maximum ripple peak-to-peak amplitude (which occurs at Vinmax) is chosen between 15% and 50% of the full load current. It is convenient to introduce a ripple factor coefficient, RF, that is therefore a number between 0.15 and 0.5. As for the linear regulator, its input voltage Vinlin should not fall below 13V and therefore the auxiliary winding should be dimensioned to get this voltage with a certain margin (say, 14V). Conversely, an higher input voltage leads to higher losses inside the regulator, to the detriment of efficiency, and to higher total current on the +3.3V inductor. Besides it implies a higher turns ratio and therefore a worse magnetic coupling, which affect energy transfer during flyback.
SWITCHING REGULATORS +5.1V Inductor To define the inductor, it is necessary to determine firstly the inductance value. Its minimum value is given by: 5.1 (Vin max - 5.1) L5min = Vin max fsw Iout5 RF and a value L5 > L5min should be selected. Core geometry selection is connected to the requirements of the specific application in terms of space utilization and other practical issues like ease of mounting, availability and so on. As to the material, the choice should be directed towards ferrite, molypermalloy or Kool M(R), to achieve high efficiency. These materials provide low core losses (ferrite in particular), so that the design can be concentrated on preventing saturation and limiting copper losses. Saturation must be avoided even at maximum peak current: IL5pk = Iout5 + 5.1 (Vin max - 5.1) 2 fsw L5 Vin max
To limit copper losses, the winding DC resistance, RL, should be as low as possible (in the range of m). AC losses can usually be neglected. A practical criterion to minimize DC resistance could be to use the largest wire that fits the selected core. Anyway the best solution, whenever possible, is to use an off-the-shelf inductor which meets the requirements in terms of inductance and maximum DC current. Nowadays there is a broad range of products
13/26
L4992
DESIGN PROCEDURE (continued) offered by manufacturer, also for surface mount assemblies. +3.3 V Transformer The primary winding carries the secondary power as well, thus the total primary average current is: Itot3 = Iout3 + Vinlin Iout12 3.3
where Vinlin is the voltage generated during the recirculation of the primary and fed into the input of the +12V linear regulator. The turns ratio 1:n of the transformer is chosen so that Vinlin is above 13V. To reduce the turns ratio in order to minimize stray parameters, the secondary is referred to the 3.3V output, and therefore the minimum value is given by: nmin = Vinlin - 3.3 + Vf 3.3
where Vf is the forward drop across the rectifier (assume 1V to be conservative). Make sure the secondary is connected with the proper polarity (see fig. 6). The minimum primary inductance value can be expressed as: L3pmin = 3.3 (Vin - 3.3)2 3 4 Vin fsw [Itot3 RF (Vin - 3.3) - n Vin Iout12]
where RF, to get positive values for L3pmin, must satisfy the inequality: RF > n Vin Iout12 Itot3 (Vin - 3.3)
and where Vin can be either Vinmin or Vinmax, whichever gives the higher value for L3pmin. With a primary inductance L3p > L3pmin the primary peak current, which must not saturate the magnetic core, will be: IL3pk = Itot3 + 3.3 (Vin max - 3.3) + n Iout12 2 fsw L3p Vin max
As to the transformer realization, the considerations regarding to the +5.1V inductor can be here repeated. Power MOSFET's and Schottky diodes Since the gate drivers of the L4992 are powered by a 5V bus , the use of logic-level MOSFET's is highly recommended, especially for high current applications. Their breakdown voltage V(BR)DSS must be greater than Vinmax with a certain margin, so the selection will address 20V or 30V devices. The RDS(ON) can be selected once the allowable power dissipation has been established. By selecting identical power MOSFET's as the main switch and the synchronous rectifier, the total power they dissipate does not depend on the duty cycle. Thus, if PON is this power loss (few percent of the rated output power), the required RDS(ON) (@ 25 C) can be derived from: RDS(ON) = PON I2 out (1 + T)
where Iout is either Itot3 or Iout5, according to the section under consideration, is the temperature coefficient of RDS(ON) (typically, = 5 10-3 C-1 for these low-voltage classes) and T the admitted temperature rise. It is worth noticing, however, that generally the lower RDS(ON), the higher is the gate charge Qg, which leads to a higher gate drive consumption. In fact, each switching cycle, a charge Qg moves from the input source to ground, resulting in an equivalent drive current: Ig = Qg fsw
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L4992
DESIGN PROCEDURE (continued) which affects efficiency at low load currents. Besides, this current is drawn from the REG5 line whose source capability, ISRC (25mA min), must not be exceeded, thus a further constraint concernes the MOSFET total gate charge (@ Vgs = 5V); ISRC , Qg 4 fSW assuming four identical MOSFET's. The Schottky diode to be placed in parallel to the synchronous rectifier must have a reverse voltage VRRM greater than Vinmax. Since it conducts for less than 5% of the switching period, the current rating can be much lower than Iout. The selection criterion should be: Vf(schottky) < Vf(body-diode) @ I = ILpk Sense Resistors The sense resistor of each section is selected according to their respective maximum output current. The current sense comparator limits the inductor peak current and therefore the maximum DC output current is the peak value less half of the peak-to-peak ripple. The intervention threshold is set at 100 mV for both sections, thus the resistor values should be: 100 [m] IL5pk 100 Rsense3 = [m] IL3pk Rsense5 = Since the comparator threshold that triggers pulse-skipping mode is 26mV, the output current at which the system enters this kind of operation is approximately one fourth of the maximum output current. The sense resistors values are in the low milliohms thus it is important to take correctly the current sense signals. Make sure that the Kelvin connections between the current sense pins of the IC and the sense resistor do not carry the output current. Input Capacitors A pulsed current (with zero average value) flows through the input capacitor of a buck converter. The AC component of this current is quite high and dissipates a considerable amount of power on the ESR of the capacitor: Vout (Vin - Vout) PCin = ESR I2 out V2 in It is easy to find that PCin has a maximum equal to (1/2) Iout (@ Vin=2 Vout, that is, 50% duty cycle). The input capacitor of each section, therefore, should be selected for a RMS ripple current rating as high as half the respective maximum output current. The capacitance value is not very important but in reality a minimum value must be ensured for stability reasons. In fact, switching regulators exhibit a negative input impedance that, at low frequencies, is: Zin(DC) = - V2 in Vout Iout
thus, if the impedance of the power source is not well below the absolute value of Zin(DC) at frequencies up to the bandwidth of the regulator control loop, there is the possibility for oscillations. To ensure stability, the following condition must be satisfied: Cin >> Leq ESRin | Zin(DC) |
where Leq is the inductance of the circuit upstream the switching regulator input and ESRin is related to the input capacitor itself. The use of high performance electrolytic capacitors is recommended. If a higher cost is of no concern, OS-CON capacitors are an excellent choice because they offer the smallest size for a given ESR or current rating. Tantalum capacitors do not tolerate pulsed current, so their use is not advisable.
15/26
L4992
DESIGN PROCEDURE (continued) Output Capacitors The output capacitor selection is based on the output voltage ripple requirements. This ripple is related to the current ripple through the inductor and is almost entirely due to the ESR of the output capacitor. Therefore, the goal is to achieve an ESR lower than a certain value, regardless of the actual capacitance value. The maximum current ripple of the +5.1V section is: IL5 = 2 (IL5pk - Iout5) considering the values obtained in the paragraph "+5.1 V Inductor". As for the +3.3V, the maximum ripple is given by: IL3 = n Iout12 Vin 3 3.3 (Vin -3.3) + Vin - 3.3 4 fsw L3p Vin
where VIN is Vinmin or Vinmax, as selected in the "+3.3V transformer" section. Anyhow, the maximum ESR will be: Vrppx ESRx ILx where the subscript x refers to either section. In pulse-skipping operation, the capacitive component of the output ripple is comparable to the resistive one, thus both should be considered: ESRX V(R) = 0.025 rppx Rsensex Lx 1 1 1 - V(C) = 3.1 10-6 rppx Coutx R2 Vin min - Vout Vout sensex If specification on the output ripple under pulse-skipping condition is also given, Coutx and ESRX must comply with it as well. Further constraints on the minimum output capacitance can arise from specifications regarding the maximum undershoot, V-out, or overshoot, V+out, due to a step-load change Iout: Cout > L I2 out
V- (Vin min Dmax- Vout) out
; Cout >
L I2 out V+ Vout out
whichever is greater, and where Dmax is the maximum duty cycle and the quantities are relevant either to the +3.3V or +5.1V section. High performance capacitors should be employed to reduce the capacitance needed for a given ESR, to avoid paralleling several parts with a considerable waste of space. Although excellent electrolytic capacitors are available, OS-CON or tantalums may be preferred especially if very compact design is required, or in case of surface mount assemblies. Multilayer ceramic capacitors with extremely low ESR are now available, but they have a large spread of the capacitance value, so they should be paralleled with another more stable, high-ESR capacitor. Miscellaneous components The feedback loop has virtually unlimited bandwidth, thus a filter is necessary to make the system insensitive to the switching frequency ripple and, in general, to prevent noise from disturbing the correct operation of the error summing comparator. Anyway, the cut-off frequency of this filter can be very high, so that line and load transient response is extremely fast. This filter is a simple R-C type where resistance and capacitance can be chosen for a typical 3dB cut-off frequency of 60 kHz. As to the bootstrap diodes, even though small signal p-n diodes might be effectively used, it is preferable to employ low-power Schottky rectifiers, since that increase slightly the gate drive voltage, in favour of efficiency. The bootstrap capacitor can be a 100nF film capacitor. The soft-start capacitors determine the time during which the current limitation circuit moves gradually the setpoint from zero up to 100 mV in order to limit the current inflow at start-up. This ramp lasts approximately 1 ms per nF of soft-start capacitance (10 to 100 nF typical values), but the actual time necessary to the output voltage to reach the steady-state value depends on the load current and the output filter capacitance. There are some critical points of the IC that may require by-pass capacitors to prevent noise from dis16/26
L4992
DESIGN PROCEDURE (continued) turbing the circuit. These points are the reference voltage VREF, the IC supply pin VIN, the REG5 line and the alternative supply pin V5SW. Use film capacitors suitable for AC decoupling.
+12 V LINEAR REGULATOR Catch Diode The diode which steers the current generated by the secondary winding of the +3.3V transformer should be a p-n fast-recovery one, with a breakdown voltage greater than: VRR = (Vinlin - 3.3) + n (V in max - 3.3) with a certain safety margin. The diode has to withstand a pulsed current whose peak value is approximately: Vin min , I13pk Iout12 Vin min - 3.3 while its RMS value is given by: I13RMS = Iout12 The DC value is obviously Iout12. Filter Capacitors The most stringent requirement on the input filter capacitor (connected between V13IN and ground) is its RMS ripple current rating, which should be at least:
Vin min
Vin min - 3.3
3.3 I13AC = Iout12 Vin min - 3.3
The working voltage should be higher than the voltage generated when the regulator is lightly loaded. Also for this part the use of high quality electrolytic or OS-CON capacitors is advised. LAYOUT AND GROUNDING The electrical design is only the first step in the development of a switching converter. Since currents ranging from Amperes to some Amperes, both DC and switched, live together on the same circuitboard, the PCB layout is vital for a correct operation of the circuit but is not an easy task. A proper layout process generally includes careful component placing, proper grounding, correct traces routing, and appropriate trace widths. Fortunately, since low voltages are involved in this kind of applications, isolation requirements are of no concern. Referring to literature for a detailed analysis of this matter, only few important points will be here reminded. 1) All current returns (signal ground, power ground, etc.) should be mutually isolated and should be connected only at a single ground point. Ground planes may be extremely useful both to arrange properly current returns and to minimize radiation (see next 2 points), even though they cannot solve every problem 2) Noise coupling between adjacent circuitry can be reduced minimizing the area of the loop where current flows. This is particularly important where there are high pulsed currents, that is the circuit including the input filter capacitor, the power switch, the synchronous rectifier and the output capacitor. The next priority should be given to the gate drive circuits. 3) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces which carry switched currents as short as possible. 4) The Kelvin-connected traces of current sense should be kept short and close together. 5) For high current paths, the traces could be doubled on the other side of the PCB whenever possible: this will reduce both the resistance and the inductance of the wiring. 6) In general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. From this viewpoint, particular care should be taken of the high impedance paths (feedback input, current sense traces...). It could be a good idea to route signal traces on one
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L4992
DESIGN PROCEDURE (continued) PCB side and power traces on the other side. 7) Use heavy copper traces: this will reduce their resistance, increasing overall efficiency and will improve their heat-sinking ability. L4992 EVAL-KIT The L4992 EVAL KIT is a fully assembled and tested demonstration board that implements a standard application circuit, configured according to the following specifications: Input Voltage Range: 6 to 25 V 3.3V Output: Iout3 = 3 A, Vrpp3 30 mV 5.1V Output: Iout5 = 3 A, Vrpp5 50 mV 12 V Output: Iout12 = 120 mA Switching frequency: fsw = 300 kHz The electrical schematic, illustrated in fig. 9, shows that some pull-up/down resistor are added to the components strictly needed in a real application. Along with a quad dip-switch, they allow to set manually the logic signals that control the chip operation. These signals are in the present case: - Switch 1: RUN5 (0= 5.1V OFF, 1= 5.1V ON) - Switch 2: NOSKIP (0= pulse-skipping ON, 1= pulse-skipping OFF) - Switch 3: OSC (0= 200 kHz, 1= 300 kHz) - Switch 4: RUN3 (0= 3.3V OFF, 1= 3.3V ON) The demonstration board is delivered with the switches configured as illustrated in fig. 8. Figure 8: Default switches configuration
0 1 1 2 3 4
Switches 1 and 4 enable/disable the two PWM sections (switch 4 manages the +12V linear regulator as well). They must be set on 1 to turn on the regulators. Please note that as long as each regulator is disabled, the relevant low-side MOSFET is in ON state. Hence, if the load is capable of sourcing current, it will be short-circuited to ground through the choke and the low-side MOS. Although the default switching frequency is 300 kHz (switch 3 set on 1) and the passive components have been selected for this frequency, the demo board will work satisfactorily at 200 kHz as well. Actually, at 200 kHz the regulators exhibit the maximum efficiency and the maximum extension of the input voltage range downwards. On the other hand, the output ripple is greater and the dynamic behaviour slightly worse. The demostration board, as it is, does not provide an interface for synchronization. Anyway, it is possible to synchronize the oscillator (with an appropriate signal: 5V amplitude pulses, spaced out by 400 ns min.), provided the switch is set on 1, simply by feeding the signal into the middle of the divider R8-R9. In this way, synchronization can be achieved at a frequency higher than 300 kHz. To synchronize the oscillator to a frequency between 200 and 300 kHz, heavier interventions on the board are needed.
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L4992
DESIGN PROCEDURE (continued) Figure 9a: Evaluation Board Circuit.
VIN=6 to 25V + C17 Q1 VOUT1 5.1V/3A R1 L1 C1 C3 D1 Q3 D3 C16 C7 C15 D4 C8 C5 C6 C2 Q4 D2 R2 C4 VOUT2 3.3V/3A Q2 D5 T1
29 6 5 4 7 R3 R5 R6 11 14 S3 C9 S4 C11
30 31
32
1
2
3 24
25
26 27
28
21 19 20
L4992
18 R7 16 15 REG12 S1 S2 R9 R8 R4 C10
8
17
9
12
13
10
22
VOUT3 12V/0.12A
C12
C13
C14
PWROK
C18
D96IN426A
Table 1: L4992 EVAL-KIT parts list
Component Resistors Refer. R1 R2 R3, R4 R5, R6, R7, R8, R9 Capacitors C1, C2 C3, C4 C5, C6, C12, C13 C7, C8, C15, C16 C9, C10, C11 C14, C18 Magnetics MOSFET's Diodes C17 L1 T1 Q1, Q2, Q3, Q4 D1, D2 D3, D4 D5 S1, S2, S3, S4 Value 25m 20m 270 1M 100F 220F 100F 1F 10nF 4.7F 15F 10H 10H Si9410DY TMBYV10-40 TMMBAT46 SMBYW01-200 Description 1%, 0.5W. DALE. p.n. WSL-2512R0251 1%, 0.5W. DALE. p.n. WSL-2512R0201 1%,SMD SMD 20V. SANYO OS-CON. p.n. 20SA100K 10V. SANYO OS-CON. p.n. 10SA220K SMD SMD SMD 16V. Tantalum. SMD 25V. SANYO OS-CON. p.n. 25SC15M 2.65A. SUMIDA. p.n. CDR125-100 1:4 ratio. TRANSPOWER. p.n. TTI5902 SILICONIX ST. MELF package ST. MINIMELF package ST.SOD6 package Quad dip-switch
Switches
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L4992
DESIGN PROCEDURE (continued) Figure 9b: PCB and component Layout of the Evaluation Board of Figure 9a.
Top Layer + Silk (56 x 61mm)
Signal Ground Plane
Power Ground Plane
Bottom Layer
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L4992
DESIGN PROCEDURE (continued) Pulse-skipping operation is enabled by default in order to maximize efficiency also in low load current range. The transition between PWM and pulse-skipping occurs approximately below 1A, however there is a region in which the two operation modes coexist rather than a definite boundary. That can be seen on the scope as an irregularity of the waveforms but does not have much influence both on output ripple and efficiency. Those who do not appreciate asynchronous operation of the pulse-skipping mode can disable it for both regulators, by setting switch 2 on 1. That maintains PWM operation up to very low output currents where, however, the regulation becomes incompatible with the switching frequency. This means that the minimum ON-time of the high-side MOSFET is too long for the thruput energy level at the operating frequency. Thus the control system begins skipping conduction cycles to avoid the output voltage drifting upwards. Table 1 shows the complete L4992 EVAL KIT parts list. Critical components characteristics are given in detail.
DEMO BOARD EVALUATION The following diagrams and tables show the typical performance of the demonstration board in terms of efficiency, line regulation and load regulation. The 12V linear regulator and REG5 are also characterized. Table 2: PWM Regulators: Optimum Efficiency
Parameter +3.3V Maximum Efficiency Test Condition RUN3 = RUN5 = HIGH, NOSKIP = LOW Vin = 6V, Iout = 0.5 A, fSW = 200 kHz Vin = 6V, Iout = 1A, fSW = 300 kHz RUN3 = LOW, NOSKIP = LOW Vin = 6V, Iout = 1A, fSW = 200 kHz Vin = 6V, Iout = 1A, fSW = 300 kHz Value 95.2 94.6 % 96.4 95.8 Unit %
+5.1V Maximum Efficiency
Table 3: PWM regulators: Line and Load Regulation.
Parameter +3.3V Line Regulation Test Condition RUN5 = LOW, NOSKIP = LOW, 6 < Vin < 20V Iout = 0.1 A, fSW = 200 kHz Iout =1A, fSW = 200 kHz RUN3 = LOW, NOSKIP = LOW, 6 < Vin < 20V Iout = 0.1A, fSW = 200 kHz Iout = 1A, fSW = 200 kHz RUN5 = LOW, NOSKIP = LOW, 5 mA < Iout < 3A Vin = 6 V, fSW = 200 kHz Vin = 15V, fSW = 200 kHz RUN3 = LOW, NOSKIP = LOW, 5 mA < Iout < 3A Vin = 6 V, fSW = 200 kHz Vin = 15V, fSW = 200 kHz Value 2 15 mV 3 20 mV 85 70 mV 90 75 Unit mV
+5.1V Line Regulation
+3.3V Load Regulation
+5.1V Load Regulation
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L4992
DEMO BOARD-EVALUATION (continued) Figure 10: 5.1V Output (RUN3=LOW, RUN5 = HIGH, OSC = GND, NOSKIP = LOW)
VO (V)
Vin=20V
D97IN579
Figure 11: 3.3V Output (RUN3=HIGH, RUN5 = LOW, OSC = GND, NOSKIP = LOW)
VO (V) 3.38
Vin=6V Vin=20V
D97IN580
5.12
5.10 5.08
Vin=6V
3.36
Vin=15V
Vin=15V
3.34
5.06 5.04 5.02
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IO(A)
3.32
3.30
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IO(A)
Figure 12: Demo Board Efficiency vs Output Current
EFF. (%)
Vin=6V
D96IN420
Figure 13: Demo Board Efficiency vs Output Current
EFF. (%)
Vin=6V
D96IN421
90
Vin=20V
90
Vin=20V
80
Vin=15V
80
Vin=15V
70
70
VO=5.1V fSW=200KHz RUN3=GND NOSKIP=GND
60
60
VO=5.1V fSW=300KHz RUN3=GND NOSKIP=GND
50
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IO(A)
50
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IO(A)
Figure 14: Demo Board Efficiency vs Output Current
EFF. (%)
Vin=6V
D96IN422A
Figure 15: Demo Board Efficiency vs Output Current
EFF. (%)
Vin=6V
D96IN423A
90
Vin=20V
90
80
80
Vin=20V
70
Vin=15V
60
VO=3.3V fSW=200KHz RUN5=GND NOSKIP=GND
70
Vin=15V
60
VO=3.3V fSW=300KHz RUN5=GND NOSKIP=GND
50
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IO(A)
50
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IO(A)
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L4992
DEMO BOARD-EVALUATION (continued) Figure 16: Demo Board Overall Efficiency (Iout3 = 3A, REG12 = OPEN, OSC = GND)
EFF. (%) 93 93 92 91 90 89
Vin=20V Vin=6V
D97IN581
Figure 17: Demo Board Overall Efficiency (Iout5 = 3A, REG12 = OPEN, OSC = GND)
EFF. (%)
Vin=6V
D97IN582
92
91
Vin=20V
88 87
0.001 0.005 0.01 0.05 0.1 0.5 1 5 IOUT5(A)
90
89
0.001 0.005 0.01 0.05 0.1 0.5 1 5IOUT3(A)
Figure 18: Switching Frequency vs Output Current (pulse skipping)
fs (KHz)
D96IN427A
Figure 19: Switching Frequency vs Output Current (pulse skipping)
fs (KHz)
D96IN428A
100
Vin=6V Vin=20V
100
Vin=6V
10
VO=3.3V REG12=OPEN OSC=2.5V
10
Vin=20V
1
1
VO=5.1V OSC=2.5V
0.1
0.001 0.005 0.01 0.05 0.1 0.5 IO(A)
0.1
0.001 0.005 0.01 0.05 0.1 0.5 IO(A)
Figure 20: REG5 Regulator Characteristic (Vin = 6V, RUN3 = RUN5 = LOW, Tj = 25C)
VOUT (V) 5.05
D97IN583
Figure 21: 12V Linear Regulator Characteristic (V13IN = 15V, RUN3 = HIGH, Tj = 25 C)
VOUT (V) 12 10
D97IN584
5.00
8 6 4
4.95
4.90
2
4.85 0 20 40 60 80 100 IOUT(mA)
0 0 50 100 150 200 IOUT(mA)
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L4992
APPLICATION IDEAS Figure 22: Application with Split Supply
12V BUS 5V BUS
C17 Q1 VOUT1 5.1V/3A R1 L1 C1 C3 D1 Q3 D3 C16 C7 C15 D4 C8 C5 C6 C2 Q4 D2 R2 C4 VOUT2 3.3V/3A Q2 D5 T1
29 6 5 4 7 R3 R5 R6 11 14 S3 C9 S4 C11
30 31
32
1
2
3 24
25
26 27
28
21 19 20
L4992
18 R7 16 15 REG12 S1 S2 R9 R8 R4 C10
8
17
9
12
13
10
22
VOUT3 12V/0.12A
C12
C13
C14
PWROK
C18
D98IN813
Figure 23: Low output voltage.
Rsense
VO <5.1V (VO <3.3V) MIN. LOAD
RB
L4992
22 RA 12V C18
6(19) 5(20) 7(18) R3(R4) C9 (C10)
D98IN814
RB BALANCES ZCD COMPARATOR
24/26
L4992
TQFP32 PACKAGE MECHANICAL DATA
DIM. MIN. A A1 A2 B C D D1 D3 e E E1 E3 L L1 K 0.45 0.05 1.35 0.30 0.09 9.00 7.00 5.60 0.80 9.00 7.00 5.60 0.60 1.00 0(min.), 7(max.) 0.75 0.018 1.40 0.37 mm TYP. MAX. 1.60 0.15 1.45 0.45 0.20 0.002 0.053 0.012 0.004 0.354 0.276 0.220 0.031 0.354 0.276 0.220 0.024 0.039 0.030 0.055 0.015 MIN. inch TYP. MAX. 0.063 0.006 0.057 0.018 0.008
D D1 D3 A1
17 16
0.10mm .004 Seating Plane
A A2
24 25
E3
E1
B
E
32 1 8
9
B C L K
e L1
TQFP32
25/26
L4992
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of SGS-THOMSON Microelectronics. (c) 1998 SGS-THOMSON Microelectronics - Printed in Italy - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - France - Germany - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A.
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